Posted with permission from Chip Scale Review Sep 2010
One of my favorite old TV series is "The Hitch Hiker’s Guide to the Galaxy" from the BBC. The story starts out when an average guy named Arthur Dent wakes up to find out that his home is about to be demolished to make way for a motorway. He is then informed by his friend Ford Prefect – who is actually an alien travel book researcher – that the Earth is about to be vaporized as part of a “Hyper-Space bypass” for extra terrestrial, faster than light-speed travelers. Many of you must now be wondering how this can possibly relate to test. Well, I think it reminds me of some of the trade-offs we face in the design and test of 3D (three dimensional) stacked packages with TSVs (through silicon vias). To make TSVs some silicon territory is being literally vaporized to make way for direct pathways between circuits on different die. A TSV might be ten or more microns in diameter, so the resulting area is large enough for a lot of digital mission-mode gates to occupy. This valuable space is sacrificed to save package and board space as well as to increase chip-to-chip signal performance; to create an effective “Hyper-space bypass” of sorts.
Today, the benefits of the TSV similarly overcome many of the evils that the process brings, including loss of silicon real-estate, because of the product benefits that come with them. However, when TSVs need to be placed for test access, the reception is not always so great because the test access path, often related to JTAG based scan architectures, does not have a lot to do with the mission mode of the devices in the stack. That is, the manufacturer doesn’t get to charge anybody for the silicon used for test access port space. It is viewed as “cost” or “expense” rather than “value added.” The result is that it makes sense to reduce the number of TSVs for test access and use the savings to reduce the area of the resulting chip design or to use the space for money-making circuits. The test access standard chosen for stacked die access will determine how much area is used for TSV connections, the physical layer of the TAP (Test Access Port), the type of ATE equipment needed, the ability to test in parallel, and the speed of test among other factors. Because the subject is evolving, complex and there are competing ideas, there is no agreed upon standard as of yet.
To help me through the fog of “if, what and maybe” for 3D testing, I called upon my old friend Al Crouch who is part of several groups who are wrestling with this topic. As always, Al overloaded my shrinking cranial capacity with masses of great information. We don’t have the space to cover it all in detail here, but what it comes down to is a couple of big architectural choices. The first choice is, given a fixed amount of test data and instructions, do you run more test access pins at moderate speed as 1149.1 JTAG tends to do today, or can we find a way to run fewer pins faster? Depending on the choice made, it’s possible to have as few as 2 pins, which connect through the stack as TSVs, or there could be more than 7 at the other extreme. Additionally, some of the architectures that use more pins require chip enable connections to select or de-select the die or function in the stack. This results in not only more area lost to TSVs, but the possibility of non-uniform test access footprint in the die stack since the enable signal might not be routed to all the die. As such, the higher pin count solutions tend to add pins to the TSV test access bus as the stack of die gets more layers. The two pin scheme can potentially stay limited to two pins in the stack because it will use packets to send test information to and from the appropriate circuit. Depending on who you talk with, packets in the test bus are either a simplification or a complication with respect to the test access circuitry. From an area standpoint, it’s quite likely the SERDES (serializer-deserializer) circuits in the two wire scheme will take up a lot less space than the TSVs of the full 1149.1 ports.
Other advantages of the two wire, packet transmission approach come at wafer sort. In some cases, the 3D device components at wafer sort may have almost no mission-mode functionality at all and scan based testing ala 1149.1 may be the only real test method for these KGDs (known good die) before assembly. That is, depending on how functionality is partitioned among the die in the stack, structural test is likely to be the only tool for creating the KGD test. Having only two pins per access port would allow more die to be tested in parallel, it reduced the probe card pins per die, and has other benefits. In fact, with some standardization of the test access and power supply pins, it may be possible to use one probe card for all the die in a stack. The more pins you use, the less likely this is. Also, remember that any pin to be probed needs to have a bonding pad as well as a TSV. This is another serious area hit.
I was able to speak with another friend who is in charge of the design of extremely large, high-performance chips at a large systems company. His chips will not have a high stack due to power, but will still use TSV for performance. Since these chips already have a couple of thousand pins and associated TSVs, the addition of a few extra TSV connections does not create an issue. However, the scalabilty of addressability native to packet signaling solutions still work out well in his case. Each of his chips might have many cores and a well designed packet architecture will help standardize the test access on each die and yet provide the flexibility to have sufficient test coverage.
In the accompanying illustration, you can see the difference in complexity between the two approaches. I am sure that a compromise will be reached by the time 3D becomes a larger percentage of shipments.
So, now you know some of the trade-offs of TSVs for test access, hyper-space bypasses and silicon motorways. Just remember, stay tuned for more developments here and as "The Hitch Hiker’s Guide to the Galaxy" said on its cover, “Don’t Panic.”