If you are in your 50s (or beyond), perhaps you are experiencing the same strange feelings that I am.  Do you occasionally long for the "good old days," when your business seemed to make more sense -- and no matter how much of a struggle it actually was, it seemed much better than it is today?

If so, you remind me of just about every old timer that I've ever met.  Does this make me (and possibly you, too?) "over the hill?"  

The Migration

The particular issue that I am bothered by now is the migration of the subcontract test companies from accommodating the test equipment requests and requirements of the fabless semiconductor companies to forcing their choices back upstream.  Let's review the three dominant test subcontractor ATE purchasing models.

Classic

The first one is "Classic."

In this mode, the subcon gets a request to purchase a particular test platform from their customer.  

With the high likelihood of substantial downstream business, but without guarantees, the subcon would buy equipment whether it was more of what they already had or based on a new platform.

It was one of the components of success for new fabless companies that needed new test technology.  It was also part of the fundamental ability of new fabless  semiconductor companies to be more flexible and outmaneuver the large IDM manufacturers.

Left Holding the Bag

The subcons have largely dumped this model.  The reason: They were left holding the bag when the industry collapsed in 2001 with lots of unsecured capacity that only recently became absorbed.

This scenario also eliminates one of the prime attractions for this model, however, which is the reduction of risk and the availability of innovation to the fabless semiconductor community.

The newest test capital trend is the "no risk to the subcon" plan.  Many subcons are refusing to adopt new platforms in most cases and are refusing to purchase extra units of existing ATE until their contracted capacity requirements are  over 100 percent of the new unit.

Refusing Business

They are actually refusing business in some cases before bringing on more capacity.  In other cases, they are having serious disagreements with their large customers before purchasing more equipment.

If you are a small customer, don't even bother having the discussion!  I have personally seen subcons tell their customers that he -- the customer -- will have to buy the new equipment and consign it at no cost.  These subcons have eliminated their role as risk moderators for fabless companies!

Shared Risk

There is a third model - the "shared risk" version.  Each side buys have the capital.  The leverage each side has is self-evident, and it is clearly the bridge between classic and no risk.

What this means is that one of the arms of flexibility and advantage for the fabless community has now been cut off.

Most fabless companies are now forced to use whatever is popular, as opposed to what is optimal.

The larger fabless companies can take matters into their own hands a bit and buy some of their own ATE, but even the largest are not usually set up for that.  Totally flexible back-end manufacturing has been a key part of their business model. 

A Brick on the Back

The no risk model is just the latest brick on the back of fabless companies.  The fabless community has already lost differentiation in wafer fab, assembly and to an extent in design.

When the history of fabless enterprise is written, I wouldn't be surprised to find that the backend subcons helped kill the fabless semiconductor companies.

Of course, the fabless companies won't just "take it" forever, either.

Instead, I suspect that as they become more frustrated with the existing subcontract test and assembly base and the new "un-service" models.  They will continue to search for new providers, and those new providers will spring from the growing markets in China and perhaps India.

I say India, because India has announced big initiatives, including a fab.  In practice, however, I suspect they will have a viable test and assembly infrastructure well ahead of their fab.

The opportunity left open by the old guard test and assembly companies will be too easy to exploit with the Indian talent pool.  The reason this will occur is that assembly and test just don't take as long to become productive as wafer fabrication plants.

Customer-Oriented

The reason that the new Indian plants will become successful is that culturally, the Indians are very customer-oriented and have a lot of well educated people with which to staff an assembly and test industry.  Finally, having a few test facilities would really complement the already existing design houses in India.

This is all conjecture, of course.  That said, it is continuing to be a world of change.  Just like our parents, we find that nothing will happen the way we want it to just because we wish it so, and this is especially true of the semiconductor economy.

Change is good, when you are on the "good side" of it, so we all continue to work to be on that side.  Still, as the bones get older, don't you wish that the ride would stay still at a comfortable spot for just a little while?

by Paul M. Sakamoto, Contributing Editor - Test [ This e-mail address is being protected from spambots. You need JavaScript enabled to view it ]

Wow, this can't be my reunion!

I'm the kind of guy who goes to his high school reunions.  I went to my 10-year reunion, and found that in general everyone seemed recognizable but with better clothes and grooming.  The 20-year reunion was a bit different in that some of us were showing signs of wear.  Overall, though, folks seemed optimistic and full of life.  After all, we were still in our thirties!

Then, I went to my 30-year high school reunion.  When I got to the appointed hotel bar, I looked around and started heading back out.  I was convinced that this must be the wrong time and place.  These old folks just could not, must not, be my high school graduating classmates.  I went back in, looked at name tags, and sure enough, these were the people and this was the place!

The IEEE International Test Conference (ITC) is the annual "high school reunion" of the test industry.  It's gone through big changes in its 38-year history, especially in the last ten.  ITC has always been the premier technical event for semiconductor test, but it was once the top commercial event as well.

But the commercial side has steadily eroded since 2000.  What was once a bustling trade show with many live demos of million-dollar test systems and thousands of folks jamming the aisles is all but gone.  The technical side has swung from presentations on esoteric hardware issues to discussions of how software is what it's all about.

An example of this sea change was this year's keynote speaker, Mike Lydon, VP of Technology and Quality for Cisco Systems.  He said, "Imagine full-circle visibility" of products through their whole usage cycle.  This is pretty much a software and design Intellectual Property (IP) strategy.  It assumes that test data comes from embedded test IP and that the real issue is to have software systems to track it all.  So much for ATE.

One company working to provide just such a tester-lite future is Asset-Intertech, a design IP company that sells solutions for test access via JTAG to all the properly IP infused chips on a board.

Logic BIST, Memory BIST, I/O BIST and other embedded test can be accessed, as well as any other "built-in" instruments in the future as long as the chips on the board support interface to JTAG.

Speaking of logic BIST, I spoke with Jim Healy, CEO of LogicVision.  His company sells IP for logic, memory and I/O BIST, and had one of the larger booths.  His emphasis is to consolidate the recent wins that they have had in memory and logic BIST and gain more ground in embedded test IP for high-speed I/O.  He views the current tough market climate as a time to "batten down the hatches" and work to complete projects, conserve cash, and gain design share in preparation for the eventual upturn.

Debbora Ahlgren, SVP and Chief Marketing Officer of Verigy, shared her views with me.  Verigy believes that software will continue to increase the full potential of their 93000 series ATE.  As an example, the Fault Insyte software they were showing allows properly configured 93000 systems to immediately display topological defect data while testing wafers in production or engineering.

A Verigy applications engineer displayed some customer correlation results between KLA-Tencor optical wafer inspection data and electrical test defects on the 93000.  The results were near-perfect, but even more impressive were the defects are found by test, not optical inspection.  These are called non-visible defects (NVDs), and they are a growing issue in the sub-65nm fabrication technologies.

Debbora's view is that Verigy will continue to create more analytical software and time-to-market aids, as well as more scalable hardware options for the 93000 platform.  This focus on a single scalable platform has resulted in large, measurable improvement in long-term cost of ownership for Verigy customers.

My discussion with Keith Lee, President of Advantest U.S.A., centered on the business environment.  He pointed out that Advantest entered this phase of the economy beng a leader in both company size and in financial strength.  Through aggressive partnering, they have been able to build on their fundamental strength in memory test and gain a major foothold in Logic and SoC.  Their success in MPU test is well known and they have recently made inroads into graphics processor units (GPUs) as well.

Advantest usually favored hardware but Keith reminded me that they are leaders in parallel test and production floor software for memories.  He believes this will pay dividends as logic and SoC test moves to high parallelism.  Regarding the recent ATE industry consolidations, Keith thought that this was a good thing in that it will bring about a more stable environment.  He said the consolidation of customer companies plays to his company's strength in catering to very large accounts.